Open Access
Issue
Int. J. Simul. Multisci. Des. Optim.
Volume 8, 2017
Article Number A6
Number of page(s) 4
DOI https://doi.org/10.1051/smdo/2016017
Published online 23 January 2017
  1. Iwamura H, Akazawa M, Amemiya Y. 1998. Single electron majority logic circuits. IEICE Trans. Electron., E81-C(1), 42–46.
  2. Dasigenis MM, Karafyllidis I, Thanailakis A. 2001. A single-electron XOR gate. Microelectron. J., 32, 117–119. [CrossRef]
  3. Ono TY, Fujiwara A, Inokawa H. 2000. Silicon single-electron devices for logic applications, in Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000), Portland, OR, USA. p. 411–420.
  4. Takahashi Y, Ono Y, Fujiwara A, Inokawa H. 2000. Multigate single-electron transistors and their application to an exclusive-OR gate. Appl. Phys. Lett., 76, 637–639. [CrossRef]
  5. Oya T, Asai T, Fukui T, Amemiya Y. 2003. A majority logic device using an irreversible single-electron box. IEEE Trans. Nanotechnol., 2(2), 15–22. [CrossRef]
  6. Rehan SE. 2007. A novel half-adder using single electron tunneling technology, in Proceedings of the 2nd IEEE International Conference on Nano/Micro Engineered and Molecular Systems, Bangkok, Thailand. p. 245–249.
  7. Zardalidis GT, Karafyllidis I. 2002. A single electron half-adder. Microelectron. J., 33, 265–269. [CrossRef]
  8. Likharev KK. 1999. Single-electron devices and their applications. Proceeding IEEE, 87(4), 606–632. [CrossRef]
  9. Tucker JR. 1992. Complementary digital logic based on the “Coulomb blockade”. J. Appl. Phys., 72(9), 4399–4413. [CrossRef]
  10. Soheili N, Bahrepour D, Loloeyan P, Navi K. 2009. A novel five-input configurable cell based on irreversible single electron box. Contemporary Engineering Sciences (CES), 2(4), 149–163.
  11. Wang C. 2015. Silicon nanowires for single slectron transistor fabrication, PhD thesis, Imperial College London. https://spiral.imperial.ac.uk/handle/10044/1/27058.
  12. Ono Y, Inokawa H, Takahashi Y, Nishiguchi K, Fujiwara A. 2010. Single‐electron transistor and its logic application. Nanotechnology, 4, 45–68.
  13. Bahrepour D, Sharifi MJ. 2010. A new single electron tunneling cell based on linear threshold gate, in Enabling Science and Nanotechnology (ESciNano), 2010 International Conference on, Kuala Lumpur. p. 1–2.
  14. Bahrepour D, Sharifi MJ. 2013. A novel high speed full adder based on linear threshold gate and its application to a 4–2 compressor. Arab. J. Sci. Eng., 38(11), 3041–3050. [CrossRef]
  15. Bahrepour D, Sharifi MJ. 2013. High speed full adder based on modified linear threshold gate and its application to a 4–2 compressor. J. Comput. Theor. Nanosci., 10(11), 2527–2535. [CrossRef]
  16. Rehan SE. 2011. The design of logic gates using Single Electron Box (SEB) nano-devices, in Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on, Athens, Greece. p. 1–6.
  17. Sharifi MJ, Bahrepour D. 2011. Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits. Microelectron. J., 42(7), 942–949. [CrossRef]
  18. Wasshuber C, Kosina H, Selberherr S. 1997. SIMON – a simulator for single-electron tunnel devices and circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 16, 937–944. [CrossRef]

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