Int. J. Simul. Multidisci. Des. Optim.
Volume 8, 2017
|Number of page(s)||4|
|Published online||23 January 2017|
Area efficient digital logic NOT gate using single electron box (SEB)
Mashhad Branch, Islamic Azad University, Mashhad, Iran
* e-mail: firstname.lastname@example.org
Accepted: 2 December 2016
The continuing scaling down of complementary metal oxide semiconductor (CMOS) has led researchers to build new devices with nano dimensions, whose behavior will be interpreted based on quantum mechanics. Single-electron devices (SEDs) are promising candidates for future VLSI applications, due to their ultra small dimensions and lower power consumption. In most SED based digital logic designs, a single gate is introduced and its performance discussed. While in the SED based circuits the fan out of designed gate circuit should be considered and measured. In the other words, cascaded SED based designs must work properly so that the next stage(s) should be driven by the previous stage. In this paper, previously NOT gate based on single electron box (SEB) which is an important structure in SED technology, is reviewed in order to obtain correct operation in series connections. The correct operation of the NOT gate is investigated in a buffer circuit which uses two connected NOT gate in series. Then, for achieving better performance the designed buffer circuit is improved by the use of scaling process.
Key words: Digital logic NOT gate / Single-electron devices (SEDs) / Fan out / Switching speed / Bit error rate / Single electron box (SEB)
© D. Bahrepour, published by EDP Sciences, 2017
This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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